1. Field of the Invention
The present invention relates generally to an analog to digital converter and is directed more particularly to a novel analog to digital converter which is high in conversion efficiency.
2. Description of the Prior Art
In the prior art, when, for example, a luminance signal is converted from analog to digital form, an analog to digital (hereinafter referred to as A/D) converter of the serial parallel type such as shown in FIG. 1 may be employed.
The prior art A/D converter shown in FIG. 1 is used to carry out the A/D conversion to produce a digital signal of 8-bits. In this case, an analog input voltage V.sub.in is applied to a first A/D converter 1 with a 3 bit output corresponding to D.sub.7 to D.sub.5 the upper 3 bits of the 8 bit representation of the Vin. This 3-bit digital output D.sub.7 to D.sub.5 is supplied to a digital to analog (hereinbelow referred to as D/A) converter 2 and then converted thereby to an analog voltage V.sub.m. This voltage V.sub.m and the input voltage V.sub.in are both applied to a subtracting circuit 3 from which a difference voltage V.sub.s =V.sub.in -V.sub.m is derived. This difference voltage V.sub.s is applied to an A/D converter 4 with a five bit output corresponding to D.sub.4 to D.sub.0, the lower 5 bits of the 8 bit representation of Vin. The digital outputs D.sub.7 to D.sub.5 and D.sub.4 to D.sub.0 are delivered through a latch 5 as an A/D converted output of 8-bits.
With the above serial-parallel type A/D converter, when the input voltage V.sub.in converted to a digital output of (m+n) bits, wherein m=3 and n=5 in the above example, that the total number of voltage comparing circuits required in the A/D converters 1 and 4 is only 2.sup.m =2.sup.n -2. Therefore, when the A/D converter is formed as an integrated circuit, the number of voltage comparing circuits and its chip size can be reduced and its power consumption can be also reduced.
With this serial-parallel type A/D converter, however, the upper bit converter 1 requires the same accuracy as that of the lower bit converter 4. The reason is as follows.
That is, suppose the digital output bits D.sub.7 to D.sub.0 are to be increased by "1" from "31" to "32". In that case, the bits D.sub.7 to D.sub.0 change from "00011111" to "00100000", so that the lower bits D.sub.4 to D.sub.0 change from "11111" to "00000", while the upper bits D.sub.7 to D.sub.5 are changed from "000" to "001". Accordingly, when the converter shown in FIG. 1 is used, and the input voltage V.sub.in is increased from "31" to "32", the outputs D.sub.7 to D.sub.5 from the converter 1 change by "1" from "000" to "001". However, when the input voltage V.sub.in is changed from the value "28" to "29" , the outputs D.sub.7 to D.sub.5 from the converter should not change from "000" to "001". This is true not only for the case when the input voltage V.sub.in is increased from "31" to "32" but also for the case when the input voltage V.sub.in is increased from "63" to "64", i.e. from 2.sup.k-1 to 2.sup.k, such that there is a carry from the bits D.sub.4 to D.sub.O to the bits D.sub.7 to D.sub.5. Further, the above is true for a case where the input voltage V.sub.in is decreased and the bits D.sub.7 to D.sub.5 are shifted to the bits D.sub.4 to D.sub.0. Accordingly, even though the converter 1 has an output of 3-bits, the converter 1 requires 5 bit accuracy just as the converter 4.
If the converter 1 does not have this accuracy, the conversion contains the above-mentioned error, and the outputs D.sub.7 to D.sub.0 do not increase regularly over at the junction between D.sub.7 to D.sub.5 and D.sub.4 to D.sub.0.
To avoid the above defect, a prior art converter such as shown in FIG. 2 is proposed which compensates for the lack of accuracy of the converter 1. In this example, the converter 4 includes an extra, redundant bit to have 6-bits, and the 6 bits D.sub.5 to D.sub.0 output therefrom are added with the outputs D.sub.7 to D.sub.5 from the converter 1 in an adding circuit 6 such that bit D.sub.5 from converter 1 and bit D.sub.5 from converter 4 have the same weight, i.e. represent the same power of 2.
According to the converter shown in FIG. 2, even if the converter 1 is poor in accuracy, the correct digital outputs D.sub.7 to D.sub.0 can be obtained from the adding circuit 6 (the reason for this is conventional and will be omitted).
In the converter shown in FIG. 2, however, since the redundant bit is added, A/D conversion of 9 bits (512 steps) is allowable, i.e. 6 bits in converter 4 and 3 bits in converter 1, but only A/D conversion of 8 bits (256 steps) is actually performed, namely a half of the capacity is wasted.